i hesitate to call gcc excellent these days, but it's definitely a head above codewarrior, which they still use over at freescale for all the old motorola and power stuff. that said, they've been working on codewarrior nearly as long as the gcc team has been working on cc, and they only have one target, really (i think they've extended it to arm, but very recently). anyway, it's fully featured now. rs08's dev env is pretty plug and play. it might even be easier than getting gcc set up for an avr target these days.
CISC is actually generally an optimized choice for small bit-widths. the downside of risc is that everything has to be explicit everywhere, but the hardware is much simpler, and at the bleeding edge of litho nodes, you can scale to much higher clocks. that's not really an issue with either of these chips. in fact, we don't even really care about mips/watt, as absolutely everything is going to fit into our power envelope.
as for ISA, an actual single processor core that's shared across all the chips means there's a chance of being able to simulate for debugging. the avr simulators are complete garbage.. actually, one of the strengths of freescale's codewarrior-based toolchain is that they've done a really good job integrating their proprietary remote debugger arch into the IDE. you can do full simulation-style debug on a running device over USB. none of this jtag uggness.
i haven't looked at the stm chips at all.. iirc they sell mostly into eg sensor nets.. hmm, i wonder if they have a small cheap soc with a lot of acmps on it.
