Can someone please check my pcb for any errors or improvements?

[EinShides]

Greeting everyone,
As the title says I was wondering if there is anyone who is willing to review my first PCB to point out any errors or improvements as I want to make sure things would work before getting it fabricated. Any advice is appreciated.
Thanks in advance.


kicad file: https://drive.google.com/file/d/1XUQPqQBZQ1Ph9lHilUNkSPab7ZEp9YVA/view?usp=sharing

[Keyboard_Warrior364]

May I suggest that you also post pictures of your schematics and pcb file if possible. Some people don't use kicad and if I'm correct, even the ones that do use it, might have trouble importing the file if they have a different version of kicad than you.

[EinShides]

Thank you for the suggestion! I have posted the pictures in the drive link below. Hopefully they are clear enough.

Pictures: https://drive.google.com/drive/folders/1i-8-KGpOeL8QCm2uxFNCrDSU_U9HrdgW?usp=sharing

[Hadi]

I definitely need to spend more time reviewing but, based on your screenshots, you should make the VCC and GND routes wider, .3 or .4mm at least. I'd also recommend moving R1 and R3 down a little to prevent any issues with the crystal. Enclosing it in a ground plane couldn't hurt, either. Otherwise, the schematic seems to be pretty identical to reference designs lying around. If you're ordering from a specific site or manufacturer, have you checked their specific design rules? 

[Applet]

Just very quick thoughts from a quick look:

• Is your GND-net called +5v? Something may be wrong here. Crystal should not be connected to +5
• USB-data traces should be routed differentially.
• I'd try and improve ground, maybe add a ground fill around MCU and crystal.

[EinShides]

Thank you both for taking the time to review the files. If you don't mind I have a few updates to show and some questions to ask.

Just very quick thoughts from a quick look:

• Is your GND-net called +5v? Something may be wrong here. Crystal should not be connected to +5
• USB-data traces should be routed differentially.
• I'd try and improve ground, maybe add a ground fill around MCU and crystal.

• My GND-net was indeed called +5v for some reason. I fixed it now.
• Could you possibly elaborate on how differently USB-data traces should be routed. Sorry, I'm a noob at this .
• I did my best to improve the ground, I don't know if this is sufficient enough though (see pictures)

I definitely need to spend more time reviewing but, based on your screenshots, you should make the VCC and GND routes wider, .3 or .4mm at least. I'd also recommend moving R1 and R3 down a little to prevent any issues with the crystal. Enclosing it in a ground plane couldn't hurt, either. Otherwise, the schematic seems to be pretty identical to reference designs lying around. If you're ordering from a specific site or manufacturer, have you checked their specific design rules? 

I took your advice and made the VCC and GND trace wider to 4mm. I don't really quite get what you mean by moving R1 and R3 down. Do you mean moving it closer to the MCU?

Anyways I hope that the changes I've made solve most of these problems. Also, if anyone could check the files again, it would be greatly appreciated. Thanks again for your time.

[Hadi]

I took your advice and made the VCC and GND trace wider to 4mm. I don't really quite get what you mean by moving R1 and R3 down. Do you mean moving it closer to the MCU?

Anyways I hope that the changes I've made solve most of these problems. Also, if anyone could check the files again, it would be greatly appreciated. Thanks again for your time.

So, this recommendation may be overkill, but those routes directly beneath your crystal can cause interference. I would divert any traces around, even if they are on other side of the board, and enclose the crystal within a ground plane for additional protection. 

[Hadi]

(Attachment Link)

Also, I think you're going to need to reroute GND now.

[EinShides]

So, this recommendation may be overkill, but those routes directly beneath your crystal can cause interference. I would divert any traces around, even if they are on other side of the board, and enclose the crystal within a ground plane for additional protection.

Thank you for the recommendation! I've moved the tracks but I don't know if this is sufficient enough. Also when I do the DRC check it says that the VCC pads and GND pads on the MCU are too close to the other pads (see markings in the picture). If I change the trace width to 0.3mm instead of 0.4mm the problem disappears. Should I be concerned about this?

[Hadi]

So, this recommendation may be overkill, but those routes directly beneath your crystal can cause interference. I would divert any traces around, even if they are on other side of the board, and enclose the crystal within a ground plane for additional protection.

Thank you for the recommendation! I've moved the tracks but I don't know if this is sufficient enough. Also when I do the DRC check it says that the VCC pads and GND pads on the MCU are too close to the other pads (see markings in the picture). If I change the trace width to 0.3mm instead of 0.4mm the problem disappears. Should I be concerned about this?

(Attachment Link)

Any design rules are subject to the capabilities of your manufacturer. Do you have an idea of how you'll be ordering and/or assembling your PCBs?

[EinShides]

Any design rules are subject to the capabilities of your manufacturer. Do you have an idea of how you'll be ordering and/or assembling your PCBs?

I was thinking either pcbway or OSH park.

[Applet]

Could you possibly elaborate on how differently USB-data traces should be routed. Sorry, I'm a noob at this .

USB data is sent differentially. In short, the combination of the two signals (D+ and D-) in the two datalines is what produces the USB data, so you need both to be timed right for the combination to be correct and you need to take care when routing these two signals. Take this with a grain of salt tho, since the USB-speed is pretty low for the MCU, it is not super critical. It's a different matter if doing high speed design, like USB3, SATA, memory etc.

Check this video:

If you want to read further, I can recommend this document: https://www.ti.com/lit/an/spraar7h/spraar7h.pdf?ts=1588577320747

I'd recommend adding gnd-vias adjacent to the crystal and decoupling capacitors. Regarding the rule violations, it should be fine, best is to update kicad rules to reflect the manufacturers capabilities.