Not an electrical engineer, but having successfully designed a boards with a duplex key matrix, I'd say it's largely irrelevant because an average scan rate of 1kHz is still considered pretty low frequency in the EE world and shouldn't cause too much trouble no matter what you do.
That said, other good design principles still apply so you generally want to minimize the trace length, amount of vias, avoid crossing over traces where not necessary, keep adequate amount of space between traces. Ideally you'd run both rows and columns on one layer in some sort of maze-like pattern with a solid ground plane underneath - but that will take time to figure out and might not even be possible depending on your design and matrix size.
But you definitely need to look at it in context of how your board is laid out, where the holes and components are placed. There's no one best solution that fits all, and unless there's nothing else on your board it'll usually need to be some sort of compromise anyway.
But like I said, given the low frequency nature of the signal it'd be very hard to really mess it up.
Less optimal layouts might cause more electromagnetic interference but this is pretty much impossible to discuss without a complete board in hand and running tests on it - which is probably also not necessary unless you're planning on mass production.
Hope this helps.
