geekhack Projects > Making Stuff Together!

[BUILD] Nyan Keys - An FPGA based USB 2.0 HS 8000hz Open Source PCB Design

(1/4) > >>

russeree:
Nyan Keys - FPGA Powered Mechanical Keyboard



Design Goal
Use an FPGA to eliminate key matrix scanning to offload the MCU and produce the lowest latency possible from switch contact to the host computer. The primary driver of this designs reduced latency is the use of USB 2.0 High-Speed (HS), which offers native support for 125Ás interrupt rates, or an 8000Hz polling rate, right out of the box without the need for additional drivers. The FPGA serves as another method to allow the MCU to focus solely on transmitting data from the keyboard to the host.

Any time I use the term "USB" in this document I am referring to USB 2.0 HS 480mb/s. This is very different than the FS and HS USB 1.1 over 2.0 implementations that exist on the market.

Nyan keys is a multi part project consisting of 3 primary parts

* Nyan Keys PCB
* Nyan OS (NOS)
* Web Config Tool
Nyan Keys PCB - By Me




Open Source Design Repos - Apache-2.0 License Github
FGPA Bitstream
Nyan OS (NOS) - STM32 Firmware
Nyan OS Config Tool - Hosted
Nyan OS Config Tool - Source
PCB Schematic and Layout

Final Features

* Lattice FPGA Ice40HX4K to handle debouncing in parallel
* STM32F723 w/ USB 2.0 HS PHY for 8000hz polling
* 1Mbit EEPROM for settings and FPGA Bitstream
Final Build

* 60% Layout w/ 2.25u shift
* Nyan Keys PCB - Oshpark Fab'd
* Kailh Box Jade Switches (3ms debounce)
* Durock V2 Stabs
* Tofu Redux (black)
* PBTFans Spark V2
Assembled




FPGA
The FPGA at the heart of Nyan Keys is used to handle the debounce of each key and high speed serialization of that data so that it can be pushed out over USB. Each key gets it's own timer core. As such all keys are parallel and do not require any diode and such! This also eliminates the need to scan a matrix since everything is happening in parallel.

The switch will arm instantly, then the state of the switch can't change until the debounce count is complete. After the count reaches the max value in [debounce time] the switch can then send over a new state instantly. What this means simply is that unless you are able to press keys at under 1ms you will not have any debounce time since the key would arm and release instantly.

The communication to the MCU that is the USB device is done via a DMA based SPI channel where 9 bytes are requested from the board at a time to represent each of the 61 keys as a binary 0 or 1. The current speed of the board can run the SPI bus at 12.5Mhz and Nyan OS can fetch a full state around 80k times a second. Which is 10x faster than what the USB bus can generate interrupts at. Using the FPGA to handle all of the debouncing instead of the MCU leaves the MCU free to send packets over USB without having to wait for any scanning to complete. This also leads into the fact that each key starts it's count instantly instead of waiting for the MCU to hit that key in it's scan pattern.

STM32F7423
MCU chosen to run Nyan OS (NOS) was the STM32F723 because of the high clock frequency and onboard USB 2.0 HS PHY. Having the onboard PHY means that there is no need for additional chips/traces to get the USB 2.0 pseudo differential signals to the STM32F& MCU. The amount of RAM is 256KB which is more than enough to handle the Nyan OS without issue whilst also allowing scancodes to be sent over to the host at the 8000hz bInterval rate. The onboard flash is also modest at 512KB and is more than enough to hold the code and string values needed. This MCU is overkill for a keyboard but because of the already high BoM costs of this board there wasn't a reason to start clipping coupons.

The MCU also has upto 16 USB endpoints of which Nyan Keys uses 2. As a USB device the Nyan Keys appears as a composite USB 2.0 HS device. The composite device consists of a CDC (Serial) endpoint used for configuration and a HID device.

NyanOS (NOS)

To facilitate an easier interface with the Nyan Keys hardware I wrote a small operating system called Nyan OS (NOS) that is able to be interacted with over serial and includes various settings right now such as getting performance stats to flashing FPGA bitstreams over serial.

Responsibilities
[*]USB 2.0 HS HID/CDC composite device
[*]Serial console via USB
[*]EEPROM master - FPGA Bitstream Storage
[*]FPGA bitstream programmer - SPI Master
[*]Status indication - 5 Leds
[*]Bitcoin Miner - Opt-In Branch Proof of Concept
[*]USB HID Interface @ 8000hz Polling
[*]SPI Master to FPGA switch serializer and debouncer
[/list]

NKRO done in a badass way thanks to USB2.0 HS
Normally NKRO has to be done using a bitmap base USB report due to the speed of the USB bus and the USB 1.1 FS limitation of 64 bytes in an interrupt packet.
None of this applies to USB 2.0 HS in any meaningful way because the interrupt packet size if 1024 bytes. Nyan Keys just sends out a HID report with 63 Bytes.
The first 8 bytes are boot compatible so you can use it for your BIOS etc. The sweet part though is with all of that extra space we can just send the rest of the
scan codes after those boot compatible bytes and it works! Nyan Keys with Nyan OS supports full NRKO at 8000hz.

NyanOS (NOS) - Web Configuration Interface



NyanOS can be controlled and configured via the Chrome web serial API. What this means is that chrome can interface with a device over serial. This means the user just has to visit russeree.github.io to start configuring their keyboard.
This website has a built in terminal to use as well as action buttons to ease the process of uploading tuned bitstreams to the FPGA.


Build Gallery








russeree:
Reserved Slot 1

russeree:
Reserved Slot 2

Limentic:
Wow, your project is so cool, I would never even thoughed about using an FPGA just to avoid a scanning matrix, but it make sense.
So overkill, but I think it's a recurring theme over here  ;D

Keep the good work!

russeree:
Thank you so much! Yeah the FPGA combined with actual USB2.0 High Speed is showing latencies of around .147-.151 milliseconds from a standard HID driver. That result was even better than my initial estimates.

The FPGA is also incredibly nice in the fact that over time users can modify and improve the design to even further reduce latency or maybe add other features such as letting the FPGA remap the keys to various layouts on the fly.

Again thanks so much for appreciating the project! Yes it's unapologetically over engineered and it was so much fun to design and build. As a note I don't even play video games, only use it for coding.

BTW: I love your magic keyboard reverse engineering!

Navigation

[0] Message Index

[#] Next page

Go to full version