Apparently, the Advantage is mostly a PS/2 keyboard with a PS/2 to USB converter tacked on. That could be a reason for it not having wake support, since it can't easily go to a low power state.
Ding ding ding.
This is pretty much exactly why I still prefer PS/2. Because all USB is doing is trying to copy it (badly) and offering nothing of significant value. I like just smacking space bar to turn on my computer.
Because PS/2 has such great low-power support, right?!
From what I can tell, a properly Energy Star compliant motherboard ought to be powering down the PS/2 port as well, in S5.
Wrong. EStar does not require depower of SuperIO unless it is A) not LPC B) cannot exclusively use 5VSB. Which is
NOT THE 5V LINE. G2(S5) mandates that 5VSB stay hot, and ACPI does not preclude WOL (magic packet) or Wake-From-Device-Arrival
unless said support requires any line other than 5VSB remain hot.
An EStar and ACPI compliant motherboard which can do power-on from PS/2 in S5 state is literally doing nothing more than using the LPC SIO as a soft switch from G2(S5) and does not go to G3 except on AC loss or specific command. EStar does not mandate G3 use. Hell, it doesn't even specify or require G2.
See here for more details.
As far as "low power" what part of "PS/2 limit is 275mA" is unclear? FYI that's less at maximum than a USB "Medium" (500mA) request, and barely over a "low" (250mA) request. Combined with the LPC SIO, you're talking about a total of around maybe 250mA-500mA (0.5A) demand for PS/2. Uh, yeah, that's less than WOL allowance.
This is a typical high end Super I/O ASIC from Nuvoton. It operates off the 3.3V line normally and is '5V tolerant' (meaning 5VSB supply capable.) It also draws a whopping 8.0mA @ 3.3V with +-10μA leakage. Pretty sure that qualifies as "low power."
By comparison, the Renesas μPD720202 USB3 host controller (2 port) requires 3.3V (so a 5VSB->3.3V or 3.3V hot), external 24MHz reference crystal, and 3.6mA
with nothing attached. A single device brings that 'low power USB3' to 148mA @ 3.3V for just the controller - excluding the USB device power draw. Yes, the controller itself draws 18.5x as much as a high end Super IO with PS/2, GPIO, UART and INT trigger capability.
Look, the problem isn't with USB - it supports low-power states just fine. PS/2 to USB converters have the problem that they don't want to add circuitry to shut off power to the PS/2 keyboard, so they can't go low-power (mine can sleep, and wake-up the PC from standby, but it breaks the rules on power).
Sigh. Why do people continually hear things I didn't say and put words in my mouth? That is beyond annoying. I'm not addressing the converter either.
What I said was
the USB controller typically resides on the chipset and requires more than 5VSB. Do
not claim I said it did not support low power. That is not what I said, period. What I also said was
in essence you cannot use USB to wake from G2(S5) because it requires more than 5VSB for the root complex - the exception being non-chipset root complexes with specific 5VSB support.
In either case, you cannot wake from a device in D3 Cold because the point of D3 Cold is that it won't do that. The EStar rules do not mandate a specific state, only capabilities, thus neither D2, D3 Hot or D3 Cold specifically violate rules. Because there's no rule for it.
Complete EStar rules for computers are here. TL;DR version is: EStar only requires capability, it does not mandate specific operation modes.
Your typical maximum source side (PSU) on 5VSB is 1A; this has to supply all 5VSB demand from both switches and motherboard components. Factoring in expected draws and efficiency losses, you end up with <200mA on a 5VSB source of 1A - before keyboard. Which means exactly what you think it does - a 1A 5VSB cannot supply an M5/M13 using double Y cable (single PS/2 on motherboard a la Gigabyte.) Yes, this makes engineering "fun."
And yes, the same token applies to USB and this is why 'charge while shut down' features mandate a 2A+ 5VSB supply. Usually runs right around 950mA (0.95A) before root complex (non-chipset, typically ASMedia, NEC/Renesas, etc.) power. Which frequently has either a dedicated 5VSB input line or a source switching circuit forward of the root complex controller. 'Supercharger' setups (>1A over USB) use in-controller limit bypass for pre-USB3 and take off the primary +5VDC or +12VDC.
As far as the peripheral side behaviors, I don't know and I stay out of that rat's nest for exactly those reasons. It is a rat's nest, there is little to no consistency despite claims to the contrary (don't even try claiming UHID is consistent with the "N-Key" hacks and 'guess if SELSUS breaks it' going on.)
The problem really seems to be with Energy Star and the definition (or interpretation?) of S5 'Soft Off'. This short thread on Intel Communities seems to sum it up - reading between the lines, manufacturers don't give a crap as long as governments will buy their stuff!
Yes, that is part of the problem. ACPI clearly defines G2 but EStar does not and doesn't care, because they attempt to lump all systems (desktop, notebook, server, etc) into a single category. Look at the actual rules - they include Game Consoles. Basically EStar is purely a marketing thing from a manufacturer and vendor standpoint. It doesn't mandate anything and the grand extent of it is their 'EZ GPO' as best practices.
EStar also doesn't use ACPI definitions because they lump in non-ACPI devices (consoles, non-x86 servers, etc) and manufacturers also need capability for non-ACPI defined states (e.g. Hot Standby S1+Global D0). I mean seriously - EStar 5.0 qualified devices include Xbox 360 (New Version), HP Integrity servers, and IBM zEnterprise. They all work off that same sheet. So yeah. EStar is pretty much worthless.
The whole policy of minimising S5 power consumption backfires because people get what they want from S3 or S4 instead, using more power overall!! For example, people wanting to be able to press space to start their machine up in the morning will just use Standby instead of Shutdown. S5 needs to be more flexible.
This is absolutely and totally wrong. On a level that scares the crap out of me. Did you not actually read the ACPI state descriptors?
S3: Suspend To RAM (STR) - maintain voltage to DRAM and related controllers (e.g. chipset, CPU) to maintain state
G2: AKA S5, Soft-Off - only 5VSB is maintained. No states are preserved.
What the hell? Seriously. They're not even comparable states, period - S3 requires 5VSB, 3.3VDC, 5VDC and 12VDC lines all remain hot. (Selected CPU registers and cache elements
must remain hot.) Albeit at a low power state, but still hot for the duration. Which is a significant amount of power draw - typically on the order of several watts. Usually around 10+ for older/low efficiency and still 4+ for high efficiency.
The whole point of S3 is that the system is still on and powered. The whole point of G2 is that the
system is off. In a G2 state with 5VSB hot and an IBM Model M attached the maximum typical draw of a 2A rated 5VSB is less than 3/4 of a watt (at 110V). You don't freaking need flexibility for G2, period, at all. The whole POINT of G2 is "system == off." If you want to boot faster from G2, get on Phoenix, Award and AMI to magically make Real mode not be 16-bit, make it faster, and/or get an SSD.
More to the point, you're pointing fingers at the wrong people with your complaints. ACPI states define
system state and do not define anything else. If I want to implement G2 and suck down so much power I need a 10A 5VSB because it's powering a dozen blinkenlights and crap? That will pass ATX and ACPI (5VSB does not have an upper bound.) If I want to use GPIO and a 3 position switch to go between S0-S3-G2 and power that exclusively off 5VSB, it will also pass.
Or to address the specific complaint: absolutely you can use a USB device to do a G2->S0 transition switch. And it will pass ATX, ACPI and EStar with flying colors. All you need is A) external root complex which can operate independent of BIOS from 5VSB, B) must maintain device in D2 or D3 Hot off 5VSB at <500mA, C) root complex must differentiate devices (e.g. UHID from Mass Storage), selectively suspend non-HID, and devices must support signalling in D3 Hot D) ability for external root complex to act as soft switch (presumably via GPIO pin) to BIOS watch lines. You have a total headroom for EStar of 2W @ 115VAC. And yes, the problem is that the manufacturers are half $&*@ing A and just not doing C or D. Mostly because external root complexes just don't do C period, because it is complex and expensive - you pretty much need a full stack to do C. In a single tiny and already complex ASIC. Adding the PROM into the silicon is bad enough - but then you get into the compatibility nightmares, because the other side of C is peripheral manufacturers. And we already know what a mixed bag that is.
So HOPEFULLY this explains why you can't do S4,G2->S0 with USB or S3->S0 with D3 Cold or Selective Suspend currently and why I HATE USB from that perspective in sufficient detail to answer ALL questions.
Yeah. Heat index of 98F (over 36C) and no A/C makes me a touch grumpy. Promise I'll be less grouchy when the weather stops being crap.
(Also possibly more coherent.)
