Cpu experts, chime in, HALP

[tp4tissue]

Mission critical build..

If a chip is tested for xxx hours bench stable @ overclock of 4.8ghz @ xxx voltage..


If I reduce the Frequency by say 300mhz and keep the voltage the same..


Would that be more stable..


VS


Lowering the voltage to meet the lower 4.5ghz




Note: "I don't care about longevity of the chip,  wear/tear"

Note: "I need to get this **** done reliably  FAST, and it doesn't scale with cores.."

I have 2x 24-core boxes, they are not faster for what I need to do.

[tbc]

yes.  the first option.

the unstability would come from the motherboard components failing from out of spec usage.

EDIT:

this is assuming you overclocked using proper methods of course....

[tp4tissue]

yes.  the first option.

the unstability would come from the motherboard components failing from out of spec usage.

Is there a particular rationale to explain one vs the other..


Experience tells me the first option is the right way to do it as well..  However I need this to be REALLY REALLY stable and the math to be sound..

[tbc]

higher voltage = taller spikes

lower frequency = wider spikes

taller and wider means bigger.


bigger spikes are easier to differentiate from other spikes, meaning that the spike showing 0 or 1 is unambigious.



ys, i know this isn't how it actually works....

[tp4tissue]

higher voltage = taller spikes

lower frequency = wider spikes

taller and wider means bigger.


bigger spikes are easier to differentiate from other spikes, meaning that the spike showing 0 or 1 is unambigious.



ys, i know this isn't how it actually works....

Hwat.....

[tbc]

i'm not going to try to explain this.

look up digital signaling

[tp4tissue]

i'm not going to try to explain this.

look up digital signaling

I know what you're trying to say..

But I was under the impression that  these voltages and timings are highly regulated.

such that the spikes wouldn't be an issue

[tbc]

i'm not going to try to explain this.

look up digital signaling

I know what you're trying to say..

But I was under the impression that  these voltages and timings are highly regulated.

such that the spikes wouldn't be an issue

the spike was a simplification, not a literal electrical spike.

when you increase the clock rate, the falling edge can sometimes get 'merged' with the rising edge of the next signal.  therefore, the 'stream' looks like 111 or 11 instead of 101.  when you increase the voltage, the edges becomes more distinct from one another.

the voltages and timings ARE calibrated at stock settings.  overclocking is literally the act of changing voltages and timings AKA intentionally uncalibrating the device.

[tp4tissue]

i'm not going to try to explain this.

look up digital signaling

I know what you're trying to say..

But I was under the impression that  these voltages and timings are highly regulated.

such that the spikes wouldn't be an issue

the spike was a simplification, not a literal electrical spike.

when you increase the clock rate, the falling edge can sometimes get 'merged' with the rising edge of the next signal.  therefore, the 'stream' looks like 111 or 11 instead of 101.  when you increase the voltage, the edges becomes more distinct from one another.

the voltages and timings ARE calibrated at stock settings.  overclocking is literally the act of changing voltages and timings AKA intentionally uncalibrating the device.

So... why doesn't the increased voltage raise  BOTH the 1s and 0s (noisefloor)  equally ?

[tbc]

i'm not going to try to explain this.

look up digital signaling

I know what you're trying to say..

But I was under the impression that  these voltages and timings are highly regulated.

such that the spikes wouldn't be an issue

the spike was a simplification, not a literal electrical spike.

when you increase the clock rate, the falling edge can sometimes get 'merged' with the rising edge of the next signal.  therefore, the 'stream' looks like 111 or 11 instead of 101.  when you increase the voltage, the edges becomes more distinct from one another.

the voltages and timings ARE calibrated at stock settings.  overclocking is literally the act of changing voltages and timings AKA intentionally uncalibrating the device.

So... why doesn't the increased voltage raise  BOTH the 1s and 0s (noisefloor)  equally ?

...?

are you sure electrical noise affects digital signal integrity?  isn't one of the fundamental points of digital signalling that it is relatively immune (given reasonable conditions)?

0 is basically just transistor leakage.

1 is the actual charge value (ya....that's probably not the actual electrical term).

EDIT:

ah, i think i understand what you mean.  afaik, the leakage increases at a non linear rate to the voltage increase.

[tp4tissue]

i'm not going to try to explain this.

look up digital signaling

I know what you're trying to say..

But I was under the impression that  these voltages and timings are highly regulated.

such that the spikes wouldn't be an issue

the spike was a simplification, not a literal electrical spike.

when you increase the clock rate, the falling edge can sometimes get 'merged' with the rising edge of the next signal.  therefore, the 'stream' looks like 111 or 11 instead of 101.  when you increase the voltage, the edges becomes more distinct from one another.

the voltages and timings ARE calibrated at stock settings.  overclocking is literally the act of changing voltages and timings AKA intentionally uncalibrating the device.

So... why doesn't the increased voltage raise  BOTH the 1s and 0s (noisefloor)  equally ?

...?

are you sure electrical noise affects digital signal integrity?  isn't one of the fundamental points of digital signalling that it is relatively immune (given reasonable conditions)?

0 is basically just transistor leakage.

1 is the actual charge value (ya....that's probably not the actual electrical term).

Ok so ur saying the readout will be immune to the larger  1s and 0s..  and errors will only increase if the  1s didn't quite make it,  or if there's not enough power to support the frequency..


So..   if I had a stock CPU, this thing's already calibrated by Intel..

I straight up give more voltage to it..     Will it be more stable ?   or will that roll-over effect  you're talking about with the 101 becoming 111 after the first tail merges...


how do I know if the  111 is happening..

[tbc]

i'm not going to try to explain this.

look up digital signaling

I know what you're trying to say..

But I was under the impression that  these voltages and timings are highly regulated.

such that the spikes wouldn't be an issue

the spike was a simplification, not a literal electrical spike.

when you increase the clock rate, the falling edge can sometimes get 'merged' with the rising edge of the next signal.  therefore, the 'stream' looks like 111 or 11 instead of 101.  when you increase the voltage, the edges becomes more distinct from one another.

the voltages and timings ARE calibrated at stock settings.  overclocking is literally the act of changing voltages and timings AKA intentionally uncalibrating the device.

So... why doesn't the increased voltage raise  BOTH the 1s and 0s (noisefloor)  equally ?

...?

are you sure electrical noise affects digital signal integrity?  isn't one of the fundamental points of digital signalling that it is relatively immune (given reasonable conditions)?

0 is basically just transistor leakage.

1 is the actual charge value (ya....that's probably not the actual electrical term).

Ok so ur saying the readout will be immune to the larger  1s and 0s..  and errors will only increase if the  1s didn't quite make it,  or if there's not enough power to support the frequency..


So..   if I had a stock CPU, this thing's already calibrated by Intel..

I straight up give more voltage to it..     Will it be more stable ?   or will that roll-over effect  you're talking about with the 101 becoming 111 after the first tail merges...

there's a reason why companies buy xeon. just sayin'

intel validates consumer cpus to some degree and adds in extra voltage by default.


basically,

if you're doing something actually mission critical, you buy a xeon and you follow intel's suggested ecosystem including ECC ram.

for all regular workstation usage, default cpu settings are fine. errors are going to be from a bad motherboard and ram.  do NOT change the voltage because adding more voltage would technically be uncalibrating it (honestly don't understand how it could mess things up though....maybe if you go overboard and extra heat affects switching speeds?)



all of the above assumes you trust intel's QA and validation departments.  i do.

[tp4tissue]

Xeon will make no difference in my app.  because I need more frequency..  I don't have 15 million dollars to pay intel to certify 1off production batches of 4ghz + xeons..

Hence this thread... hahaha


Now this "discalibria" you're talking about..  at what point is m0re voltage harmful,  If I can sacrifice the chip for only a few months operation..

[tbc]

Xeon will make no difference in my app.  because I need more frequency..  I don't have 15 million dollars to pay intel to certify 1off production batches of 4ghz + xeons..

Hence this thread... hahaha


Now this "discalibria" you're talking about..  at what point is m0re voltage harmful,  If I can sacrifice the chip for only a few months operation..

i would guess something that looks relatively linear.....

i would imagine you need actual hard measurements of physical components to calculate.

maybe an electrician can guesstimate?

[tp4tissue]

Xeon will make no difference in my app.  because I need more frequency..  I don't have 15 million dollars to pay intel to certify 1off production batches of 4ghz + xeons..

Hence this thread... hahaha


Now this "discalibria" you're talking about..  at what point is m0re voltage harmful,  If I can sacrifice the chip for only a few months operation..

i would guess something that looks relatively linear.....

i would imagine you need actual hard measurements of physical components to calculate.

maybe an electrician can guesstimate?

[Oobly]

In theory, keeping the voltage the same and lowering the frequency SHOULD result in more stability, but it's not always the case.

I have OC'd a number of CPU's and some of them were LESS stable at lower clocks and the same voltage. With many of them you find a "sweet spot" where the voltage and frequency just like to sit.

But 1 is more likely to be true than 2, so I'd keep the voltage up while dropping the frequency.

[Hiroyuki]

Technically speaking, lowering the frequency should reduce the chance of errors in a CMOS-circuit - IF the circuit doesn't incur any timing violations and the like at this reduced frequency. Lowering the frequency also reduces heat, albeit by a much smaller amount than lowering the voltage would (Voltage relates exponentially to the power dissipation of the circuit, while frequency relates linearly). Lower temperature = less current leakage of the transistors = larger noise margins in the circuit. keeping voltage above spec it shouldn't lead to stability problems unless something gets too hot (for example, the cache part of the i7 Nehalem CPU (I am not sure about the newer ones) do not have temperature monitors, so your temperature might be far out of spec on that part of the die, while within spec on the core logic)

Also you should take into consideration that no two CPUs are identical - there are fabrication differences between to physical CPUs due to the extremely small scale they are produced, so one condition that might apply to one CPU will not necessarily apply to the next (although of course they tend to be similar)